With the rising level of integration in semiconductor devices and integrated circuits and with higher device densities, there has been a growing demand for multilayer structures, particularly in semiconductor device elements. This trend toward higher integration results in narrower line spacings, leading to the problem of wire delay due to the increased capacitance between lines (see Japanese Patent Publication No. 3585384).
More specifically, although declines in signal propagation speed due to the parasitic capacitance of dielectric films have hitherto been known to occur, in generations of semiconductor devices with line spacings of more than 1 μm, wire delay had only a small effect on the device as a whole. However, at line spacings of 1 μm or less, the effect of wire delay on device speed increases; in particular, when circuits come to be formed at line spacings of 0.1 μm or less, the parasitic capacitance between lines will exert a large influence on device speed.
Wire delay (T) is affected both by the line resistance (R) and the capacitance (C) between lines, as illustrated by formula (4) below.T∝CR  (4)In formula (4), the relationship between ∈ (dielectric constant) and C is depicted in formula (5).C=∈o∈rS/d  (5)In formula (5), S is the electrode surface area, ∈o is the dielectric constant of a vacuum, ∈r is the dielectric constant of the dielectric film, and d is the line spacing.
Hence, lowering the dielectric constant of the dielectric film is an effective way to make the wire delay smaller.
At present, low dielectric constant dielectric films in semiconductor devices and integrated circuits are primarily made of silicon compound-based materials. However, when a silicon compound-based material is etched in the process of forming multilayer wiring, the surface becomes hydrophilic, leading to a rise in the dielectric constant due to the influence of water adsorption thereto (etching damage), a rise in the dielectric constant due to etching residues, and a deterioration in adhesion with overlying layers. These are impediments to high-speed operation and high reliability in semiconductor devices and integrated circuits (see Japanese Patent Application Laid-open No. 2001-33988).
It is therefore an object of the present invention to provide an agent for the post-etch treatment of silicon-based dielectric films, which agent is able to suppress a rise in the dielectric constant of the silicon-based dielectric film. Other objects and advantages of the invention will become apparent from the following description.